High performance 25 nm gate CMOSFETs for 65 nm node high speed MPUs

Author

Goto, K. ; Tagawa, Y. ; Ohta, H. ; Morioka, H. ; Pidin, S. ; Momiyama, Y. ; Kokura, H. ; Inagaki, S. ; Tamura, N. ; Hori, M. ; Mori, T. ; Kase, M. ; Hashimoto, K. ; Kojima, M. ; Sugii, T.

Author_Institution

Fujitsu Ltd., Tokyo, Japan

fYear

2003

fDate

8-10 Dec. 2003

Abstract

Aggressively scaled 25 nm gate CMOSFETs for the 65 nm node are reported. We successfully improved the short channel effect while keeping a high drive current by using total process controls (SW, offset-spacer, extension, halo, mechanical stress, etc.). Both mobility in nMOS and NBTI in pMOS are improved by combination of low temperature annealing and oxynitride gate oxide with low nitrogen concentration. High drive currents of 840/1010 /spl mu/A//spl mu/m and CV/I values of 0.54/0.60 psec with 25/33 nm gate nMOSFETs were achieved at Vdd=1 V and Ioff=100 nA//spl mu/m. They are the best values among recent published papers.

Keywords

CMOS integrated circuits; MOSFET; dielectric thin films; doping profiles; electric current; integrated circuit design; integrated circuit measurement; ion implantation; microprocessor chips; process control; semiconductor device measurement; silicon compounds; 1 V; 25 nm; 33 nm; 65 nm; SD-extension optimization; SiON-Si; drive current; halo implanted deceivers; high speed MPU; low nitrogen concentration; low temperature annealing; mechanical stress; nMOS mobility; offset-spacer; oxynitride gate oxide; pMOS NBTI; scaled gate CMOSFET; short channel effect; total process controls; Annealing; CMOSFETs; MOS devices; MOSFETs; Niobium compounds; Nitrogen; Process control; Stress; Temperature; Titanium compounds;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2003. IEDM '03 Technical Digest. IEEE International

Conference_Location

Washington, DC, USA

Print_ISBN

0-7803-7872-5

Type

conf

DOI

10.1109/IEDM.2003.1269358

Filename

1269358