A highly manufacturable low power and high speed HfSiO CMOS FET with dual poly-Si gate electrodes

Author

Iwamoto, Takuya ; Ogura, Tsuneo ; Terai, M. ; Watanabe, Hiromi ; Watanabe, Hiromi ; Ikarashi, N. ; Miyamura, Makoto ; Tatsumi, Taizo ; Saitoh, Masatoshi ; Morioka, Ayuka ; Watanabe, K. ; Saito, Yuya ; Yabe, Yuhei ; Ikarashi, T. ; Masuzaki, K. ; Mochizuki,

Author_Institution

Silicon Syst. Res. Labs., NEC Corp., Kanagawa, Japan

fYear

2003

fDate

8-10 Dec. 2003

Abstract

For 90 nm node poly-Si gated MISFETs with HfSiO (1.8 nm) insulator, a nearly symmetrical set of Vths for NFET and PFET: (0.38 V and -0.46 V, respectively) have been realized for low power device operation. The key technology is the suppression of Vth instability in PFETs arising from oxidation of the poly-Si/HfSiO interface, combined with channel engineering for the PFET. Our poly-Si/HfSiO gate-stacked CMOSFETs realize low I/sub off/ (N/PFET: 4.8/3.6 pA//spl mu/m) and high I/sub on/ (N/PFET: 469/140 /spl mu/A//spl mu/m) at V/sub DD/=1.2 V. Further, for SRAM cell using this CMOS, normal operation has been achieved.

Keywords

CMOS integrated circuits; MOSFET; SRAM chips; elemental semiconductors; hafnium compounds; low-power electronics; silicon; silicon compounds; -0.46 V; 0.38 V; 1.2 V; 1.8 nm; 90 nm; HfSiO CMOS FET; MISFET; NFET; PFET; SRAM cell; Si-HfSiO; channel engineering; dual poly-Si gate electrodes; gate-stacked CMOSFET; high speed FET; insulator; interface oxidation; low power CMOS; threshold voltage instability suppression; CMOS technology; CMOSFETs; Electrodes; FETs; Insulation; MISFETs; Manufacturing; Oxidation; Power engineering and energy; Random access memory;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2003. IEDM '03 Technical Digest. IEEE International

Conference_Location

Washington, DC, USA

Print_ISBN

0-7803-7872-5

Type

conf

DOI

10.1109/IEDM.2003.1269362

Filename

1269362