Author :
Tavel, B. ; Bidaud, M. ; Emonet, N. ; Barge, D. ; Planes, N. ; Brut, H. ; Roy, D. ; Vildeuil, J.C. ; Difrenza, R. ; Rochereau, K. ; Denais, M. ; Huard, V. ; Llinares, P. ; Bruyere, S. ; Parthasarthy, C. ; Revil, N. ; Pantel, R. ; Guyader, F. ; Vishnubotla
Abstract :
This work shows the benefits of using plasma nitrided gate oxide which supports the gate leakage requirements for 65 nm platform development. Electrical data shows gate leakage to be reduced by half a decade compared to conventional NO processing with Ioff at 3nA/um, Vdd=0.9 V for 65 nm general purpose requirements. Extensive device characterization of the plasma nitride process is presented where the reduction in gate leakage offers benefits in terms of a 4/spl times/ reduction in static power, a 6% reduction in dynamic power consumption, comparative analog performance and improved reliability.
Keywords :
CMOS integrated circuits; leakage currents; mixed analogue-digital integrated circuits; nitridation; plasma materials processing; 0.9 V; 65 nm; digital CMOS; gate leakage reduction; mixed-signal CMOS; plasma nitrided gate oxide; thin oxynitride gate; Annealing; CMOS technology; Dielectric measurements; Energy consumption; Gate leakage; High-K gate dielectrics; Nitrogen; Plasma devices; Plasma materials processing; Ring oscillators;
