DocumentCode :
259068
Title :
Conflict-free FFT circuit using loop architecture by 5-bank memory system
Author :
Nishitsuji, Takashi ; Kakue, Takashi ; Shimobaba, Tomoyoshi ; Ito, Tomoyoshi
Author_Institution :
Grad. Sch. of Eng., Chiba Univ., Chiba, Japan
fYear :
2014
fDate :
17-20 Nov. 2014
Firstpage :
523
Lastpage :
526
Abstract :
We developed " Loop architecture " which can perform different length FFT without changing fundamental circuit composition. In order to perform FFT effectively, we adopted Mixed-radix FFT algorithm with radix-2 and radix-4 butterfly calculation. Furthermore, we developed " Pipelined butterfly calculation system" and "5-bank memory architecture" in order to perform Mixed-radix FFT effectively. As a result, we succeeded to develop the versatile FFT processing system with small circuit area and low latency. In addition, we implemented our circuit to Spartan-6 FPGA board and developed sound analysis system via USB.
Keywords :
fast Fourier transforms; field programmable gate arrays; hypercube networks; peripheral interfaces; random-access storage; FFT processing system; Spartan-6 FPGA board; USB; circuit composition; conflict-free FFT circuit; fast Fourier transforms; field programmable gate arrays; loop architecture; memory architecture; memory system; mixed-radix FFT algorithm; pipelined butterfly calculation system; radix-2 butterfly calculation; radix-4 butterfly calculation; sound analysis system; Control systems; Field-flow fractionation; Indexes; Memory architecture; Radiation detectors; Random access memory;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems (APCCAS), 2014 IEEE Asia Pacific Conference on
Conference_Location :
Ishigaki
Type :
conf
DOI :
10.1109/APCCAS.2014.7032834
Filename :
7032834
Link To Document :
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