DocumentCode :
259076
Title :
Secure scan design using improved random order and its evaluations
Author :
Oya, Masaru ; Atobe, Yuta ; Youhua Shi ; Yanagisawa, Masao ; Togawa, Nozomu
Author_Institution :
Dept. of Comput. Sci. & Commun. Eng., Waseda Univ., Tokyo, Japan
fYear :
2014
fDate :
17-20 Nov. 2014
Firstpage :
555
Lastpage :
558
Abstract :
Scan test using scan chains is one of the most important DFT techniques. However, scan-based attacks are reported which can retrieve the secret key in crypto circuits by using scan chains. Secure scan architecture is strongly required to protect scan chains from scan-based attacks. This paper proposes an improved version of random order as a secure scan architecture. In improved random order, a scan chain is partitioned into multiple sub-chains. The structure of the scan chain changes dynamically by selecting a subchain to scan out. Testability and security of the proposed improved random order are also discussed in the paper, and the implementation results demonstrate the effectiveness of the proposed method.
Keywords :
design for testability; fault diagnosis; private key cryptography; DFT techniques; crypto circuits; improved random order; scan chains; scan test; scan-based attacks; secret key; secure scan architecture; secure scan design; Electrical fault detection; Fault detection; Logic gates; Multiplexing; Security; Vectors; scan chains; scan-based attack; secure cryptro circuit; secure scan architecture;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems (APCCAS), 2014 IEEE Asia Pacific Conference on
Conference_Location :
Ishigaki
Type :
conf
DOI :
10.1109/APCCAS.2014.7032842
Filename :
7032842
Link To Document :
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