DocumentCode :
2590859
Title :
Diagnostic and detection fault collapsing for multiple output circuits
Author :
Sandireddy, Raja K K R ; Agrawal, Vishwani D.
Author_Institution :
Dept. of Electr. & Comput. Eng., Auburn Univ., AL, USA
fYear :
2005
fDate :
7-11 March 2005
Firstpage :
1014
Abstract :
We discuss fault equivalence and dominance relations for multiple output combinational circuits. The conventional definition for equivalence says that "two faults are equivalent if and only if the corresponding faulty circuits have identical output functions". This definition, which is based on indistinguishability of the faults, is extended for multiple output circuits as "two faults of a Boolean circuit are equivalent if and only if the pair of the output functions is identical at each output of the circuit". This is termed as diagnostic equivalence in this paper. "If all tests that detect a fault also detect another fault, not necessarily on the same output, then the two faults are called detection equivalent". Two detection equivalent faults need not be indistinguishable. The definitions for fault dominance follow on similar lines. A novel algorithm based on redundancy identification has been proposed to find the equivalence and dominance collapsed sets based on diagnostic and detection collapsing. Applying the algorithm to a 4-bit ALU would collapse the total fault set of 502 faults to 253 and 155, respectively, according to diagnostic equivalence and dominance. The collapsed sets have 234 and 92 faults, respectively, for detection equivalence and dominance. In comparison, the traditional structural equivalence and dominance collapsing results in 301 and 248 faults, respectively. Finally, we use library-based functional collapsing in a hierarchical system and find that smaller fault sets are obtained with an order of magnitude reduction in CPU time for very large circuits.
Keywords :
automatic test pattern generation; combinational circuits; fault diagnosis; integrated circuit reliability; integrated circuit testing; logic testing; redundancy; 4 bit; ALU; ATPG; Boolean circuit; CPU time magnitude reduction; detection equivalent faults; detection fault collapsing; diagnostic equivalence; diagnostic fault collapsing; dominance collapsed sets; equivalence collapsed sets; fault dominance relations; fault equivalence; fault indistinguishability; faulty circuit output functions; hierarchical system; library-based functional collapsing; multiple output circuits; redundancy identification; structural dominance collapsing; structural equivalence; total fault set collapse; Automatic test pattern generation; Central Processing Unit; Circuit faults; Circuit testing; Combinational circuits; Electrical fault detection; Fault detection; Hierarchical systems; Redundancy;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design, Automation and Test in Europe, 2005. Proceedings
ISSN :
1530-1591
Print_ISBN :
0-7695-2288-2
Type :
conf
DOI :
10.1109/DATE.2005.121
Filename :
1395722
Link To Document :
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