Framework for fault analysis and test generation in DRAMs

Author

Al-Ars, Zaid ; Hamdioui, Said ; Mueller, Georg ; Van de Goor, Ad J.

Author_Institution

CatRam Solutions, Delft, Netherlands

fYear

2005

fDate

7-11 March 2005

Firstpage

1020

Abstract

With the increasing complexity of memory behavior, attempts are being made to come up with a methodical approach that employs electrical simulation to tackle the memory test problem. This paper describes a framework of algorithms and tools developed jointly by the Delft University of Technology and Infineon Technologies to systematically generate DRAM tests using Spice simulation. The proposed Spice-based test approach enjoys the advantage of being relatively inexpensive, yet highly accurate in describing the desired memory faulty behavior.

Keywords

DRAM chips; SPICE; automatic test pattern generation; circuit simulation; failure analysis; fault diagnosis; integrated circuit testing; logic simulation; DRAM; Spice simulation; Spice-based test approach; electrical simulation; fault analysis framework; memory behavior complexity; memory faulty behavior; memory test; test generation; test generation framework; Analytical models; Computational modeling; Failure analysis; Laboratories; Manufacturing; Packaging; Performance evaluation; Random access memory; Testing; Wafer scale integration; DRAM testing; defect simulation; faulty behavior; test generation; tool framework;

fLanguage

English

Publisher

ieee

Conference_Titel

Design, Automation and Test in Europe, 2005. Proceedings

ISSN

1530-1591

Print_ISBN

0-7695-2288-2

Type

conf

DOI

10.1109/DATE.2005.161

Filename

1395723