DocumentCode :
259090
Title :
High-voltage tolerant switch configuration using standard 3.3-V 0.5-μm silicon-on-sapphire CMOS transistors
Author :
Alex, Asish Zac ; Lehmann, Torsten
Author_Institution :
Sch. of Electr. Eng. & Telecommun., Univ. of New South Wales., Sydney, NSW, Australia
fYear :
2014
fDate :
17-20 Nov. 2014
Firstpage :
591
Lastpage :
594
Abstract :
This paper presents the design for a high-voltage tolerant switch that finds application in systems with three times the supply voltage. The design is done using silicon-on-sapphire (SOS) technology CMOS transistors to utilize the advantages of the lack of parasitic issues and high speed. The design provides a method to minimize costs as it uses only standard CMOS transistors which lower manufacturing costs by avoiding expensive transistor modification methods. The design also reduces the leakage through auxiliary control circuits by employing tracking switches compared to MOS connected diodes. The proposed switch has an efficiency of 90% when used as an output driver for a load of 830μA. All performance simulations are done on cadence software customized by the Peregrine Semiconductor Corporation.
Keywords :
CMOS integrated circuits; field effect transistor switches; semiconductor device reliability; silicon-on-insulator; Peregrine Semiconductor Corporation; SOS technology; auxiliary control circuits; cadence software; current 830 muA; efficiency 90 percent; high-voltage tolerant switch configuration; silicon-on-sapphire CMOS transistors; size 0.5 mum; tracking switches; voltage 3.3 V; CMOS integrated circuits; Implants; Logic gates; Standards; Switches; Switching circuits; Transistors;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems (APCCAS), 2014 IEEE Asia Pacific Conference on
Conference_Location :
Ishigaki
Type :
conf
DOI :
10.1109/APCCAS.2014.7032850
Filename :
7032850
Link To Document :
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