Impact of on-chip interconnects on vertical signal propagation in 3D ICs

Three-dimensional integrated circuits (3D ICs) provide a promising solution for overcoming delay/power problems of 2D ICs by stacking chips vertically. Signal propagation speed among the stacked chips is very important for 3D IC systems. We propose a simple model for analyzing the vertical signal propagation in through-silicon-via-based 3D ICs and discuss the impact of physical parameter variations on propagation delay. Experimental results show that on-chip interconnects greatly affect vertical signal propagation when there are dense general interconnects near the vertical signal interconnect, large amount of fanout, and interconnect length of a driver and receivers is long.