DocumentCode
2591084
Title
A high density, low on-resistance 700V class trench offset drain LDMOSFET (TOD-LDMOS)
Author
Teranishi, H. ; Kitamura, A. ; Watanabe, Y. ; Ogino, M. ; Sugahara, Y. ; Kajiwara, S. ; Mochizuki, K. ; Wakimoto, S. ; Iwaya, M. ; Fujishima, N.
Author_Institution
Device Technol. Lab., Fuji Electr. Adv. Technol. Co., Ltd., Nagano, Japan
fYear
2003
fDate
8-10 Dec. 2003
Abstract
We present a low on-resistance 700 V class trench offset drain LDMOSFET. A Noffset drain region is formed around the oxide-filled trench whose width and depth are both 20 /spl mu/m. The fabricated MOSFET exhibits a specific on-resistance of 10.4 /spl Omega/ mm/sup 2/, which is about 30% lower than the experimental best record so far.
Keywords
isolation technology; power MOSFET; 20 micron; 700 V; Noffset drain region; high density TOD-LDMOS; low on-resistance LDMOSFET; oxide-filled trench; trench offset drain LDMOSFET; Application specific integrated circuits; Breakdown voltage; Etching; Fabrication; Laboratories; Low voltage; MOSFET circuits; Oxidation; Power integrated circuits; Silicon;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting, 2003. IEDM '03 Technical Digest. IEEE International
Conference_Location
Washington, DC, USA
Print_ISBN
0-7803-7872-5
Type
conf
DOI
10.1109/IEDM.2003.1269391
Filename
1269391
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