A new method for the design of Digital Disciplined

Disciplined clock has been widely used as a result of many fine features such as high precision, low cost and so on. In this paper, we designed a scheme implementing the digital phase-locked loop based on the primary principles of the disciplined clock system. This scheme constructs a high-resolution phase detector using the good autocorrelation characteristics of pseudo-random code, and measures phase difference. And using this scheme a GPS disciplined clock test system is designed. The actual measurement results show that this method can improve local 1PPS output long-term stability.