Title :
An 8 Gbps, 4:1 transition-aware self-toggling multiplexer
Author :
Wei-Zen Chen ; Yi-Hung Yang
Author_Institution :
Dept. of Electron. Eng., Nat. Chiao-Tung Univ., Hsinchu, Taiwan
Abstract :
A novel 8Gbps, 4:1 transition aware multiplexer (MUX) is proposed. The multiplexer core is basically a self-toggling TSPC flip-flop, which is deactivated when no data transition is detected. The high speed serial data is regenerated by gating the triggered clock. It combines the advantages of data retiming to eliminate deterministic jitter. Besides, the short clock-to-Qb delay enables high speed multiplexing. Power reduction can be achieved by deactivating the power hungry flip-flop thanks to the random probability of data transition. Fabricated in 55 nm CMOS technology, the core circuit occupies a chip area of 77 × 81μm2 only. It dissipates 10.3 mW from a 1.2 V supply.
Keywords :
CMOS logic circuits; flip-flops; jitter; low-power electronics; multiplexing; CMOS technology; bit rate 8 Gbit/s; data retiming; data transition random probability; deterministic jitter elimination; high speed multiplexing; high speed serial data; multiplexer core; power 10.3 mW; power reduction; self-toggling TSPC flip-flop; self-toggling multiplexer; short clock-to-Qb delay; size 55 nm; size 77 mum; size 81 mum; transition aware multiplexer; voltage 1.2 V; CMOS integrated circuits; Clocks; Delays; Detectors; Flip-flops; Jitter; Multiplexing; TSPC; clock gating; dynamic flip flop; multiplexer;
Conference_Titel :
Circuits and Systems (APCCAS), 2014 IEEE Asia Pacific Conference on
Conference_Location :
Ishigaki
DOI :
10.1109/APCCAS.2014.7032867
