Considering circuit observability don´t cares in CNF satisfiability

Boolean satisfiability (SAT) has seen significant use in various tasks in circuit verification. A key contributor to the efficiency of contemporary SAT solvers is fast deduction using Boolean constraint propagation (BCP). This can be efficiently implemented with a conjunctive normal form (CNF) representation of a circuit. However, most circuit verification tasks start from a logic circuit description of the problem instance. A simple conversion from a logic circuit to a CNF (Tseitin, G.S., 1968), that enables the use of the CNF representation even for circuit verification tasks, loses some information regarding the structure of the circuit. One example of such structural information is circuit observability don´t cares. Several recent papers have addressed the issue of handling circuit unobservability in CNF-based SAT, but none of them accurately captures the conditions for use of this information in all stages of a CNF-based SAT solver. To take such don´t care information into consideration in a CNF-based SAT solver, we propose a broader approach that adds certain don´t care literals to clauses in the CNF representation. These literals are treated differently at different times during the solution process, much like don´t cares in logic synthesis. The major merit of this scheme is that the solver can continue to use this don´t care information during the learning process, which is an important part of contemporary SAT solvers. We have implemented this approach in the zChaff SAT solver and experiments show that significant performance gain can be obtained.