A systematic network-on-chip traffic modeling and generation methodology

The Network-on-chip (NoC) based multiprocessor system-on-chip (MPSoCs) is becoming a promising architecture to meet modern applications´ ever-increasing demands for computing capability under limited power budget. NoC traffic patterns are essential tools for NoC performance assessment and architecture design exploration. In this paper, we present a systematic NoC traffic modeling and generation methodology and a set of realistic NoC traffic patterns called MCSL, which are generated through the methodology. The proposed methodology can faithfully capture both the communication behaviors of real applications in NoCs and the temporal dependencies among them. And it optimizes application memory requirements, mapping and scheduling to maximize overall system performance and utilization before extracting traffic patterns through cycle-level simulations. Extensive experiments are conducted to verify the effectiveness of the methodology, and evaluate the performance of the generated traffic patterns. The results show that the MCSL traffic patterns can be used to study NoC characteristics more accurately than traditional random traffic patterns.