Title :
90-nm-node multi-level AG-AND type flash memory with cell size of true 2 F/sup 2//bit and programming throughput of 10 MB/s
Author :
Sasago, Y. ; Kurata, H. ; Arigane, T. ; Otsuga, K. ; Kobayashi, T. ; Ikeda, Y. ; Fukumura, T. ; Narumi, S. ; Sato, A. ; Terauchi, T. ; Shimizu, M. ; Noda, S. ; Kozakai, K. ; Tsuchiya, O. ; Furusawa, K.
Author_Institution :
Central Res. Lab., Hitachi Ltd., Kokubunji, Japan
Abstract :
The first true 2-F/sup 2//bit flash cell with a programming throughput of 10 MB/s was developed. In this cell, diffusion-layer local bit lines of an assist-gate AND-type flash are replaced by inversion-layer ones under assist gates. The bit-line pitch is thus reduced to 2 F. A drain-disturbance-free and soft-write-free flash cell was produced by means of a new diffusion-layer-less technology. Source-side injection programming is applicable to the new flash cell; therefore, the cell programming time is reduced to 1 /spl mu/s. The smallest memory cell (0.0162 /spl mu/m/sup 2//bit) achieved to date was accomplished by using a 90-nm technology node and applying multi-level cell technology.
Keywords :
flash memories; 1 mus; 10 MB/s; 90 nm; assist-gate AND-type flash; bit-line pitch; cell programming time; diffusion-layer local bit lines; inversion-layer bit lines; memory cell size; multi-level AG-AND flash memory; multi-level cell technology; programming throughput; source-side injection programming; Electronic mail; Electrons; Flash memory; Intrusion detection; Isolation technology; Laboratories; Silicon; Throughput; Voltage;
Conference_Titel :
Electron Devices Meeting, 2003. IEDM '03 Technical Digest. IEEE International
Conference_Location :
Washington, DC, USA
Print_ISBN :
0-7803-7872-5
DOI :
10.1109/IEDM.2003.1269406
