• DocumentCode
    2591459
  • Title

    Reconfigurable linear decompressors using symbolic Gaussian elimination

  • Author

    Balakrishnan, Kedarnath J. ; Touba, Nur A.

  • Author_Institution
    Comput. Eng. Res. Center, Texas Univ., Austin, TX, USA
  • fYear
    2005
  • fDate
    7-11 March 2005
  • Firstpage
    1130
  • Abstract
    A methodology for designing a reconfigurable linear decompressor is presented. A symbolic Gaussian elimination method to solve a constrained Boolean matrix is proposed and utilized for designing the reconfigurable network. The proposed scheme can be implemented in conjunction with any decompressor that has a combinational linear network. Using the given linear decompressor as a starting point, the proposed method improves the compression further. A nice feature of the proposed method is that it can be implemented with very little hardware overhead. Experimental results indicate that significant improvements can be achieved.
  • Keywords
    Boolean algebra; Gaussian processes; combinational circuits; data compression; integrated circuit testing; matrix algebra; chip testing; combinational linear network; constrained Boolean matrix; reconfigurable linear decompressors; reconfigurable network; symbolic Gaussian elimination; test data compression; Automatic testing; Bandwidth; Circuit testing; Design engineering; Design methodology; Hardware; Memory; National electric code; Test data compression; Vectors;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design, Automation and Test in Europe, 2005. Proceedings
  • ISSN
    1530-1591
  • Print_ISBN
    0-7695-2288-2
  • Type

    conf

  • DOI
    10.1109/DATE.2005.255
  • Filename
    1395746