Title :
High performance 90/65nm BEOL technology with CVD porous low-k dielectrics (k/spl sim/2.5) and low-k etching stop (k/spl sim/3.0)
Author :
Wu, Z.C. ; Chou, T.J. ; Lin, S.H. ; Huang, Y.L. ; Lin, C.H. ; Li, L.P. ; Chen, B.T. ; Lu, Y.C. ; Chiang, C.C. ; Chen, M.C. ; Chang, W. ; Jang, S.M. ; Liang, M.S.
Author_Institution :
Dept. of Dielectric & CMP, Taiwan Semicond. Manuf. Co., Hsinchu, Taiwan
Abstract :
Successful integration of high performance Cu dual damascene interconnects (DDIs) using a low-k etch stop (LES, oxygen-doped carbide, k/spl sim/3.0) and a porous low-k IMD (OSG, k/spl sim/2.5) has been demonstrated for the first time. The Cu DDIs with the LES not only revealed excellent resistance to stress induced voiding (SIV) but also exhibited 21% better interconnect RC delay, 100% higher via-EM endurance, 100 times lower line-line leakage at 125/spl deg/C, and 5% faster device operation speed as compared to the DDIs with a currently used etch stop (CES, oxygen-doped carbide, k/spl sim/4.5).
Keywords :
chemical vapour deposition; copper; dielectric thin films; integrated circuit interconnections; integrated circuit metallisation; leakage currents; porous materials; 125 degC; 90 to 65 nm; CES; CVD porous low-k dielectrics; Cu; Cu dual damascene interconnects; DDI; IMD; LES; OSG; SIV; high performance BEOL technology; interconnect RC delay; line-line leakage; low-k etching stop; oxygen-doped carbide; stress induced voiding; via-EM endurance; Delay; Dielectrics; Electronics industry; Etching; Industrial electronics; Integrated circuit interconnections; Manufacturing industries; Research and development; Semiconductor device manufacture; Stress;
Conference_Titel :
Electron Devices Meeting, 2003. IEDM '03 Technical Digest. IEEE International
Conference_Location :
Washington, DC, USA
Print_ISBN :
0-7803-7872-5
DOI :
10.1109/IEDM.2003.1269412
