Title :
Robust porous MSQ (k=2.3, e=12 GPa) for low-temperature (<350/spl deg/C) Cu/low-k integration using ArF resist mask process
Author :
Ohashi, N. ; Misawa, K. ; Sone, S. ; Shin, H.J. ; Inukai, K. ; Soda, E. ; Kondo, S. ; Furuya, A. ; Okamura, H. ; Ogawa, S. ; Kobayashi, N.
Author_Institution :
Semicond. Leading Edge Technol. Inc., Ibaraki, Japan
Abstract :
Towards the 65 nm technology node, Cu interconnects using a high-modulus and low-temperature porous MSQ (methyl silsesquioxane, k=2.3) process has been developed. With an advantage of a lower k value, this process is fairly compatible with the 90 nm-node technology in terms of mechanical strength of low-k film, low thermal budget to suppress SIV (stress induced void) failures, and a use of conventional ArF resist mask process. Good electrical results were obtained for 300-mm-wafer Cu dual damascene interconnects using low-pressure CMP and advanced Cu-electroplating/barrier metal processes.
Keywords :
chemical mechanical polishing; copper; dielectric thin films; electroplating; integrated circuit interconnections; integrated circuit metallisation; mechanical strength; organic compounds; porous materials; 12 GPa; 300 mm; 65 nm; 90 nm; ArF; ArF resist mask process; Cu; Cu-electroplating; SIV suppression; barrier metal processes; dual damascene interconnects; high-modulus MSQ process; low-pressure CMP; low-temperature Cu/low-k integration; mechanical strength; methyl silsesquioxane; porous MSQ; stress induced void failures; thermal budget; Chemicals; Curing; Dry etching; Lead compounds; Leakage current; Resists; Robustness; Semiconductor films; Thermal resistance; Thermal stresses;
Conference_Titel :
Electron Devices Meeting, 2003. IEDM '03 Technical Digest. IEEE International
Conference_Location :
Washington, DC, USA
Print_ISBN :
0-7803-7872-5
DOI :
10.1109/IEDM.2003.1269414
