• DocumentCode
    2591629
  • Title

    RNS approach to adaptive Burg algorithm

  • Author

    Cardarilli, G.C. ; Lojacono, R. ; Salerno, M.

  • Author_Institution
    Dept. of Electron. Eng., Rome Univ., Italy
  • fYear
    1988
  • fDate
    13-17 Jun 1988
  • Firstpage
    130
  • Lastpage
    133
  • Abstract
    Digital signal processing using the residue number system (RNS) is an area of renewed and growing research interest. A basic difficulty is the division required by most of the adaptive algorithms. The authors propose a method to implement a unified RNS architecture for both product and general division. The architecture of a whole RNS Burg cell and the layout of the main blocks in a 1.5 μm p-well CMOS technology are presented. The RNS realization is compared with a classical NMOS implementation previously developed by the authors
  • Keywords
    CMOS integrated circuits; computerised signal processing; digital arithmetic; integrated logic circuits; 1.5 micron; RNS approach; adaptive Burg algorithm; digital signal processing; p-well CMOS technology; residue number system; Adaptive algorithm; Arithmetic; Digital signal processing; Digital signal processing chips; Lattices; MOS devices; Parallel architectures; Remote sensing; Signal processing algorithms; Time factors;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electrotechnics, 1988. Conference Proceedings on Area Communication, EUROCON 88., 8th European Conference on
  • Conference_Location
    Stockholm
  • Type

    conf

  • DOI
    10.1109/EURCON.1988.11122
  • Filename
    11122