Effect of substrate contacts on reducing crosstalk noise between TSVs

We propose a model for coupling that considers substrate contacts between through silicon vias (TSVs) in bulk-CMOS technologies. The proposed model is compact but has reasonable accuracy for the dense substrate contacts in large-scale three dimensional integrated circuits (3D ICs). We describe the modeling for substrate contacts with the equivalent electrical circuit, discuss the impact of substrate contacts on the electrical parasitic parameters, and clarify the effect of substrate contacts on reducing crosstalk noise and increasing delay. Results of analysis show that if substrate contacts are not considered, crosstalk noise becomes the overestimate of 5 to 700 times and delay becomes the underestimate of 1.4 to 2.4 times.