Fast turn around post process yield enhancement for custom VLSI foundries

Author

Parks, H.G.

Author_Institution

Dept. of Electr. & Comput. Eng., Arizona Univ., Tucson, AZ, USA

fYear

1990

fDate

11-12 Sep 1990

Firstpage

82

Lastpage

87

Abstract

An effective fast-turnaround postprocess yield-enhancement methodology for custom VLSI which has been developed using a static random access memory (SRAM) and a test element group (TEG) yield vehicle is described. The SRAM/TEG is combined on a single chip providing a unified process-control vehicle. Several examples of visual defect classification using SRAM failure analysis and nonvisual defect characterization from the electrical test monitors are presented. Application of the methodology to yield enhancement efforts for a 1.25-μm process is presented showing excellent correlation of SRAM and custom circuit yields with a 100× defect density reduction over a two-year period

Keywords

SRAM chips; VLSI; failure analysis; integrated circuit manufacture; integrated circuit testing; SRAM failure analysis; correlation; custom VLSI foundries; custom circuit yields; fast-turnaround; nonvisual defect characterization; post process yield enhancement; process-control vehicle; static random access memory; test element group; Foundries; Inspection; Integrated circuit yield; Process control; Random access memory; SRAM chips; Scanning electron microscopy; Testing; Vehicles; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Advanced Semiconductor Manufacturing Conference and Workshop, 1990. ASMC 90 Proceedings. IEEE/SEMI 1990

Conference_Location

Danvers, MA

Type

conf

DOI

10.1109/ASMC.1990.111225

Filename

111225