DocumentCode
2591780
Title
Statistical bin limits: an approach to wafer dispositioning in IC fabrication
Author
Illyes, S. ; Baglee, David
Author_Institution
Intel Corp., Rio Rancho, NM, USA
fYear
1990
fDate
11-12 Sep 1990
Firstpage
95
Lastpage
98
Abstract
The methodology of selecting and implementing statistical bin limits (SBLs) for wafer-level testing is discussed. Improvements in the manufacturing flow are discussed. It is found that SBLs can detect process shifts, reject misprocessed material, aid in the streamlining of packaged units, and increase the cost effectiveness of these units. It is shown that the methodology does not add to the complexity of the sort flow. Implementation and maintenance are straightforward and simple
Keywords
integrated circuit manufacture; integrated circuit testing; production testing; statistical process control; IC fabrication; cost effectiveness; manufacturing flow; packaged units; process shifts; sort flow; statistical bin limits; wafer dispositioning; wafer-level testing; CMOS process; Circuit testing; Costs; Drives; EPROM; Fabrication; Input variables; Integrated circuit reliability; Integrated circuit testing; Monitoring;
fLanguage
English
Publisher
ieee
Conference_Titel
Advanced Semiconductor Manufacturing Conference and Workshop, 1990. ASMC 90 Proceedings. IEEE/SEMI 1990
Conference_Location
Danvers, MA
Type
conf
DOI
10.1109/ASMC.1990.111228
Filename
111228
Link To Document