DocumentCode
2591783
Title
A design of a capacitorless 1T-DRAM cell using gate-induced drain leakage (GIDL) current for low-power and high-speed embedded memory
Author
Yoshida, E. ; Tanaka, T.
Author_Institution
Fujitsu Labs. Ltd., Akiruno, Japan
fYear
2003
fDate
8-10 Dec. 2003
Abstract
A capacitorless 1T DRAM cell using gate-induced drain leakage (GIRL) current for write operation was demonstrated for the first time. Compared with the conventional write operation with impact ionization current, write operation with GIDL current provides low-power and high-speed operation. The capacitorless 1T-DRAM is the most promising technology for high performance embedded DRAM LSI.
Keywords
DRAM chips; MOSFET; leakage currents; low-power electronics; silicon-on-insulator; GIDL current write operation; SOI-NMOSFET; capacitorless 1T-DRAM cell; embedded DRAM LSI; gate-induced drain leakage current; high-speed memory; low-power memory; Degradation; Dielectric devices; Energy consumption; Hot carrier injection; Impact ionization; Laboratories; Large scale integration; Random access memory; Threshold voltage; Tunneling;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting, 2003. IEDM '03 Technical Digest. IEEE International
Conference_Location
Washington, DC, USA
Print_ISBN
0-7803-7872-5
Type
conf
DOI
10.1109/IEDM.2003.1269427
Filename
1269427
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