Title :
A design of a capacitorless 1T-DRAM cell using gate-induced drain leakage (GIDL) current for low-power and high-speed embedded memory
Author :
Yoshida, E. ; Tanaka, T.
Author_Institution :
Fujitsu Labs. Ltd., Akiruno, Japan
Abstract :
A capacitorless 1T DRAM cell using gate-induced drain leakage (GIRL) current for write operation was demonstrated for the first time. Compared with the conventional write operation with impact ionization current, write operation with GIDL current provides low-power and high-speed operation. The capacitorless 1T-DRAM is the most promising technology for high performance embedded DRAM LSI.
Keywords :
DRAM chips; MOSFET; leakage currents; low-power electronics; silicon-on-insulator; GIDL current write operation; SOI-NMOSFET; capacitorless 1T-DRAM cell; embedded DRAM LSI; gate-induced drain leakage current; high-speed memory; low-power memory; Degradation; Dielectric devices; Energy consumption; Hot carrier injection; Impact ionization; Laboratories; Large scale integration; Random access memory; Threshold voltage; Tunneling;
Conference_Titel :
Electron Devices Meeting, 2003. IEDM '03 Technical Digest. IEEE International
Conference_Location :
Washington, DC, USA
Print_ISBN :
0-7803-7872-5
DOI :
10.1109/IEDM.2003.1269427
