Title :
Critical assessment of soft breakdown stability time and the implementation of new post-breakdown methodology for ultra-thin gate oxides [MOSFET]
Author :
Wu, E. ; Sune, J. ; Linder, B. ; Stathis, J. ; Lai, W.
Author_Institution :
Microelectron. Div., IBM Corp., Essex Junction, VT, USA
Abstract :
The reliability margin seriously shrinks when gate oxide thickness is scaled below 2 nm. In this work we pursue a general picture of the breakdown in ultra-thin oxides by studying the statistics of the residual time, T/sub res/, defined as the time elapsed between the occurrence of the first breakdown (T/sub BD/) and the time of device failure. We have found that a classification of the breakdown events into SBD (soft breakdown) and HBD (hard breakdown) is still meaningful in oxides with thickness down to 1 nm, although both modes finally cause the transistor failure after a certain stress time. The obtained results have allowed us to develop a reliability methodology that includes, in a general framework, the device failure by three different processes: i) progressive HBD; ii) degradation of SBD into HBD and iii) superposition of several successive SBD events.
Keywords :
MOSFET; dielectric thin films; failure analysis; semiconductor device breakdown; semiconductor device measurement; semiconductor device reliability; statistical analysis; 1 nm; first breakdown/device failure time; gate oxide post-breakdown methodology; hard breakdown; oxide thickness; reliability; soft breakdown stability time; transistor failure; ultra-thin gate oxides; CMOS technology; Degradation; Digital circuits; Electric breakdown; Low voltage; Microelectronics; Residual stresses; Stability; Statistics; Transistors;
Conference_Titel :
Electron Devices Meeting, 2003. IEDM '03 Technical Digest. IEEE International
Conference_Location :
Washington, DC, USA
Print_ISBN :
0-7803-7872-5
DOI :
10.1109/IEDM.2003.1269428