Title :
Spread and folded architectures for FFT
Author :
Vacher, André ; Guyot, Alain
Author_Institution :
CNRS, Univ. Joseph Fourier, Grenoble, France
Abstract :
Computing a Fourier transform with a parallel architecture of serial operators needs a lot of implementation area to obtain the high performances promised with this method. Allocating processors to each step of the computation or computing only one step at the same time is one of the problems to solve. The degree of integration of up-to-date chips promises a realistic implementation of such solutions. Accuracy, area, computation time are the parameters to study before choosing a method in relation to the number of samples of the working space
Keywords :
fast Fourier transforms; parallel architectures; FFT; Fourier transform; folded architectures; parallel architecture; processor allocation; spread architectures; Arithmetic; Computer aided manufacturing; Computer architecture; Concurrent computing; Data flow computing; Laboratories; Parallel architectures;
Conference_Titel :
System Theory, 1995., Proceedings of the Twenty-Seventh Southeastern Symposium on
Conference_Location :
Starkville, MS
Print_ISBN :
0-8186-6985-3
DOI :
10.1109/SSST.1995.390540
