Title :
A 0.18 /spl mu/m 4Mb toggling MRAM
Author :
Durlam, M. ; Addie, D. ; Akerman, J. ; Butcher, B. ; Brown, P. ; Chan, J. ; DeHerrera, M. ; Engel, B.N. ; Feil, B. ; Grynkewich, G. ; Janesky, J. ; Johnson, M. ; Kyler, K. ; Molla, J. ; Martin, J. ; Nagel, K. ; Ren, J. ; Rizzo, N.D. ; Rodriguez, T. ; Savt
Author_Institution :
Motorola Semicond. Products Sector, Motorola Labs., Tempe, AZ, USA
Abstract :
A low power 4Mb Magnetoresistive Random Access Memory (MRAM) with a new magnetic switching mode is presented for the first time. The memory cell is based on a 1-Transistor 1-Magnetic Tunnel Junction (1TIMTJ) bit cell. The 4Mb MRAM circuit was designed in a five level metal, 0.18/spl mu/m CMOS process with a bit cell size of 1.55/spl mu/m/sup 2/. A new cell architecture, bit structure, and switching mode improve the operational performance of the MRAM as compared to conventional MRAM. The 4Mb circuit is the largest MRAM memory demonstration to date.
Keywords :
CMOS memory circuits; magnetoresistive devices; random-access storage; tunnelling magnetoresistance; 4 Mbit; CMOS process; bit structure; cell architecture; low power MRAM; magnetic switching mode; magnetic tunnel junction; magnetoresistive random access memory; nonvolatile memory; scalability; switching mode; toggling MRAM; write programming; Bismuth; CMOS technology; Circuits; Delay lines; Isolation technology; Magnetic cores; Magnetic separation; Random access memory; Solids; Very large scale integration;
Conference_Titel :
Electron Devices Meeting, 2003. IEDM '03 Technical Digest. IEEE International
Conference_Location :
Washington, DC, USA
Print_ISBN :
0-7803-7872-5
DOI :
10.1109/IEDM.2003.1269448
