Proceedings. Design, Automation and Test in Europe

The following topics are dealt with: partitioning and optimisation for reconfigurable computing; SoC design-for-test; low power design; scheduling and synthesis for reconfigurable computing; analogue simulation, placement and statistical analysis; analogue and gigahertz test; ubiquitous computing; power aware design in DSM technology; analogue, mixed-signal and RF circuits; reliability at the very deep sub-micron region; IP-based design; HW/SW solutions for low power multimedia systems; embedded systems; logic synthesis; defect detection and characterisation; real-time scheduling; SoC power optimisation; system level languages, verification and simulation; reliable memory design; execution-time analysis; CMOS design; high-level verification; system modelling with UML; parallel and multithreaded processor architectures; very deep submicron simulation; SoC prototyping and simulation; memory optimisation and clocking for SoC; test power reduction; multiprocessor embedded systems; layout issues; pattern generation for fault detection and diagnosis; embedded software technology; advanced analogue performance modelling; SAT based verification; test pattern compression and delay test schemes; compiler/architecture codesign; network-on-chip design flows; biochips and quantum computing; CMOS-based biosensor arrays; network-on-chip architectures; concurrent error detection and correction; formal verification of processor architecture and DSP programs; interconnect optimisation; media and signal processing; secure and embedded security systems; MPSoC platforms; low-power wireless LANs; wireless communication and networking; automotive applications; IP-reuse; design verification; sensors.