Title :
A practical method for high-level synthesis of combinational logic from VHDL
Author :
Morton, Greg ; Haggard, Roger L.
Author_Institution :
Dept. of Electr. Eng., Tennessee Technol. Univ., Cookeville, TN, USA
Abstract :
This paper demonstrates a method to allow rapid design from a high level VHDL program down to a simple netlist. Each stage of the design process generates a complete design representation as the behavioral axis of the Y-chart is descended. These design representations can be simulated to verify operation at each stage. The result is a fast and efficient method for digital design
Keywords :
combinational circuits; formal verification; hardware description languages; high level synthesis; logic design; VHDL; Y-chart; behavioral axis; combinational logic; design process; design representation; high level VHDL program; high-level synthesis; simple netlist; Algorithm design and analysis; Arithmetic; Design methodology; Equations; Hardware; High level synthesis; Logic; Object oriented modeling; Process design; Variable structure systems;
Conference_Titel :
System Theory, 1995., Proceedings of the Twenty-Seventh Southeastern Symposium on
Conference_Location :
Starkville, MS
Print_ISBN :
0-8186-6985-3
DOI :
10.1109/SSST.1995.390555
