Area efficient hardware implementation of elliptic curve cryptography by iteratively applying Karatsuba´s method

Securing communication channels is especially needed in wireless environments, but applying cipher mechanisms in software is limited by the calculation and energy resources of mobile devices. If hardware is applied to realize cryptographic operations, cost becomes an issue. We describe an approach which tackles all three of these points. We implemented a hardware accelerator for polynomial multiplication in extended Galois fields (GF) applying Karatsuba´s method iteratively. With this approach, the area required is reduced to 2.1 mm² in comparison to 6.2 mm² for the standard application of Karatsuba´s method, i.e., for its recursive application. Our approach also reduces the energy consumption to 60 per cent of the original approach. The price we have to pay for this achievement is an increased execution time. In our implementation, a polynomial multiplication takes 3 clock cycles, whereas the recursive Karatsuba approach needs only one clock cycle. However, considering area, energy and calculation speed, we are convinced that the benefits of our approach outweigh its drawback.