Fast and accurate transaction level modeling of an extended AMBA2.0 bus architecture

Author

Kim, Young-Taek ; Kim, Taehun ; Kim, Youngduk ; Shin, Chulho ; Chung, Eui-Young ; Choi, Kyu-Myung ; Kong, Jeong-Taek ; Eo, Soo-Kwan

Author_Institution

Syst. LSI, Samsung Electron. Co., Ltd., Gyeonggi-Do, South Korea

fYear

2005

fDate

7-11 March 2005

Firstpage

138

Abstract

A transaction level modeling (TLM) approach is used to meet the simulation speed as well as cycle accuracy for large scale SoC performance analysis. We implemented the transaction-level model of a proprietary bus called AHB+ which supports an extended AMBA2.0 protocol. The AHB+ transaction-level model is shown to be 353 times faster than the pin-accurate RTL model, while maintaining 97% accuracy on average. We also present the TLM development procedure of a bus architecture.

Keywords

asynchronous circuits; integrated circuit modelling; logic simulation; protocols; quality of service; system buses; system-on-chip; AHB+ bus; QoS; TLM development procedure; arbitration algorithms; bus architecture transaction level modeling; bus protocol; cycle accuracy; extended AMBA2.0 bus architecture; large scale SoC performance analysis; simulation speed; transaction level modeling; Automatic testing; Communication system control; Computer aided engineering; Design automation; Europe; Filters; Large scale integration; Protocols; Research and development; Signal design;

fLanguage

English

Publisher

ieee

Conference_Titel

Design, Automation and Test in Europe, 2005. Proceedings

ISSN

1530-1591

Print_ISBN

0-7695-2288-2

Type

conf

DOI

10.1109/DATE.2005.152

Filename

1395809