2593339

Using VHDL for Link to Synthesis Tools

Belhadj, Mohammed

IRISA

1994

30 Jun-1 Jul 1994

Computer aided engineering; Delay; Design automation; Hardware; High level synthesis; Joining processes; Signal design; Signal generators; Signal processing; Signal synthesis;

English

ieee

Test Workshop, 1994. ATW '94. The Third Annual Atlantic

conf

10.1109/ATW.1994.747844

747844