DocumentCode
2594240
Title
4×2Gbps Source-Synchronous Transmitter in 45nm CMOS
Author
Kamath, Anant S. ; Sinha, Vikas ; Chakravarty, Sujoy
Author_Institution
Analog Interfaces & Sub-Syst., Texas Instrum. India Pvt. Ltd., Bangalore, India
fYear
2011
fDate
2-7 Jan. 2011
Firstpage
1
Lastpage
5
Abstract
A 4-lane, 2Gbps-per-lane, source synchronous, voltage-mode differential transmitter is presented here. Staggered switching of driver termination is used to obtain controlled, nearlinear rise/fall transitions on the pads. The timing for the staggering is generated by a calibrated digitally controlled delay line. An on-chip high bandwidth regulator serves as a low impedance 400mV source required for voltage mode transmission. The transmitter, designed and fabricated in 45nm CMOS technology, occupies a core area of 0.013mm2 per lane and consumes 4.3mW/Gbps.
Keywords
CMOS integrated circuits; delay lines; digital control; driver circuits; transmitters; CMOS technology; delay line; digital control; driver termination; size 45 nm; source synchronous transmitter; voltage 400 mV; voltage-mode differential transmitter; Calibration; Delay; Driver circuits; Impedance; Regulators; Synchronization; Transmitters;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design (VLSI Design), 2011 24th International Conference on
Conference_Location
Chennai
ISSN
1063-9667
Print_ISBN
978-1-61284-327-8
Electronic_ISBN
1063-9667
Type
conf
DOI
10.1109/VLSID.2011.33
Filename
5718768
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