An 87 pico-second cmos variable delay line incorporating the parallel-resonator loads in K-band

Summary form only given, as follows. This paper reports a variable delay line (VDL) with a tuning range of the group delay (GD) higher than 87 ps in K-band. Our theoretical derivations show that the reflection load in the parallel form can make the reflection-type VDL achieve wider tuning range of the GD than those of the reflection load in the series form. A practical prototype of the VDL is fabricated by using CMOS 0.13 um 1P8M processes. The measured tuning range of the GD confirms the predictions given by the design equations.