• DocumentCode
    2594946
  • Title

    A Reconfigurable Processor for Phylogenetic Inference

  • Author

    Liu, Pei ; Hemani, Ahmed ; Paul, Kolin

  • Author_Institution
    Dept. of ES, KTH (R. Inst. of Technol.), Stockholm, Sweden
  • fYear
    2011
  • fDate
    2-7 Jan. 2011
  • Firstpage
    226
  • Lastpage
    231
  • Abstract
    A reconfigurable processor tailored for accelerating Phylogenetic Inference is proposed. In this paper, a programmable and scalable architectural platform instantiates an array of coarse grained light weight processing elements and allows arbitrary partitioning and scheduling schemes and capable of solving complete Maximum Likelihood algorithm and deal with arbitrarily large sequences. The key difference of the proposed CGRA based solution compared to FPGA and GPU based solutions is a much better match of the architecture and algorithm for the core computational need as well as the system level architectural need. For the same degree of parallelism, we provide a 2.27X speed-up improvements compared to FPGA with the same amount of core logic, and an 81.87X speed-up improvements compared to GPU with the same silicon area respectively.
  • Keywords
    biocomputing; bioinformatics; computer graphic equipment; coprocessors; evolution (biological); field programmable gate arrays; genetics; maximum likelihood estimation; reconfigurable architectures; 2.27X speed up improvement; 81.87X speed up improvement; CGRA based solution; FPGA; GPU; arbitrary partitioning; coarse grained light weight processing element; maximum likelihood algorithm; phylogenetic inference; programmable architectural platform; reconfigurable processor; scalable architectural platform; scheduling scheme; silicon area; system level architecture; Algorithm design and analysis; Arrays; DNA; Field programmable gate arrays; Phylogeny; Proteins; Coarse Grain Reconfigurable Architecture; Maximum Likelihood Algorithm; Phylogenetic Inference; Phylogenetic Likelihood Function; VLSI;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Design (VLSI Design), 2011 24th International Conference on
  • Conference_Location
    Chennai
  • ISSN
    1063-9667
  • Print_ISBN
    978-1-61284-327-8
  • Electronic_ISBN
    1063-9667
  • Type

    conf

  • DOI
    10.1109/VLSID.2011.74
  • Filename
    5718806