DocumentCode
2595059
Title
Hazard-Aware Directed Transition Fault ATPG for Effective Critical Path Test
Author
Devanathan, V.R. ; Shah, Ishaan Santhosh
Author_Institution
Texas Instrum. (India) Pvt. Ltd., Bangalore, India
fYear
2011
fDate
2-7 Jan. 2011
Firstpage
262
Lastpage
267
Abstract
Aggressive speed and voltage binning schemes are widely used in the industry to combat process variation. Generating structural tests that are effective for speed and voltage binning is very important to reduce cost and improve quality. We observe that hazards are common along critical paths of many industrial designs and conventional path-delay ATPG is ineffective for paths with static hazards. We propose a directed transition fault ATPG scheme that works with commercial ATPG tools to test the critical paths with hazards. The proposed scheme is implemented on industrial designs and silicon results are presented.
Keywords
VLSI; automatic test pattern generation; elemental semiconductors; silicon; Si; aggressive speed; critical path test; hazard-aware directed transition fault ATPG; industrial designs; silicon; structural tests; voltage binning schemes; Automatic test pattern generation; Circuit faults; Delay; Hazards; Logic gates; Silicon;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design (VLSI Design), 2011 24th International Conference on
Conference_Location
Chennai
ISSN
1063-9667
Print_ISBN
978-1-61284-327-8
Electronic_ISBN
1063-9667
Type
conf
DOI
10.1109/VLSID.2011.42
Filename
5718812
Link To Document