BCH-based compactors with data compression

This paper presents a novel approach to compacting a test response for a multiple scan chains design. The compactor design is based on extended an (n+1, k) BCH code, where k is the number of information bits and n+1 is the number of bits in the block. It can detect any odd number of single-bit errors and up to 2 t single-bit errors, where t is a positive integer, n-k les mt, and n+1 = 2^m. Also we use a controllable mask to handle any number of unknown logic values (Xs) on test responses. We show how additional data can be reduced by proposed compression technique. Compared to augmenting previous space compaction techniques with additional circuitry to mask any number of Xs, our approach can detect more single-bit errors with minimum number of compactor outputs. This leads to fewer tester channels, shorten test application time, and smaller test data volumes regardless of the circuit under test (CUT) and fault models.