Title :
Fault Collapsing Using a Novel Extensibility Relation
Author :
Chandrasekar, Maheshwar ; Hsiao, Michael S.
Author_Institution :
Dept. of Electr. & Comput. Eng., Virginia Tech, Blacksburg, VA, USA
Abstract :
Fault Collapsing of a target fault-list can help in obtaining a compact test set, decreasing test-generation/fault simulation time, and indirectly reducing test data volume and test application time during Manufacturing Test. These factors have a direct impact on test economics, thus obtaining a compact fault list is essential. In this paper, we propose a novel extensibility relation that aids in identifying non-trivial dominance relationships among fault-pairs. We show that our technique supersedes existing dominance-based collapsing techniques and thus may identify more dominance relations among faults. To this end, we learn several necessary assignments for faults in a low-cost fault independent manner, in which memory requirements are also low. Further, from a theoretical point of interest, we theorize a lower bound on the size of a collapsed fault-list. Experimental results on ISCAS85 and full-scan versions of ISCAS89 circuits indicate that, on an average, our technique can eliminate 5% of faults from the collapsed fault list reported by the best known fault collapsing engine. Further, our technique consumed only 2% - 4% of the memory used by the best known engine, which also provided for a 2:3× average speed-up!
Keywords :
fault simulation; integrated circuit testing; extensibility relation; fault collapsing; manufacturing test; target fault-list; Automatic test pattern generation; Benchmark testing; Circuit faults; Engines; Fault diagnosis; Fires; Logic gates;
Conference_Titel :
VLSI Design (VLSI Design), 2011 24th International Conference on
Conference_Location :
Chennai
Print_ISBN :
978-1-61284-327-8
Electronic_ISBN :
1063-9667
DOI :
10.1109/VLSID.2011.56