Title :
Current-mode CMOS adders using multiple-valued logic
Author :
Radanovic, Bob ; Syrzycki, Marek
Author_Institution :
Sch. of Eng. Sci., Simon Fraser Univ., Burnaby, BC, Canada
Abstract :
In this paper we report on initial development stages of two designs of current-mode multiple-valued logic (CMMVL) adders utilizing a positive digit (PD) number representation. The first design is the adder cell that uses the radix-2 algorithm and seven levels of current, fabricated in 0.8 μm CMOS technology, with a unit current step of 12 μA. The second design is a 4-digit decimal adder that uses a standard algorithm for adding decimal numbers represented by 10 current levels, with a unit current step equal to 1 μA, fabricated in 1.5 μm CMOS technology. The adder requires 4 input terminals compared to 10 terminals necessary for the same function implemented in binary logic
Keywords :
CMOS analogue integrated circuits; CMOS logic circuits; adders; analogue processing circuits; arithmetic; multivalued logic circuits; 0.8 micron; 1.5 micron; 4-digit decimal adder; MVL adders; current-mode CMOS adders; multiple-valued logic; positive digit number representation; radix-2 algorithm; Adders; Algorithm design and analysis; CMOS logic circuits; CMOS technology; Complexity theory; Logic circuits; Logic design; Mirrors; Switches; Voltage;
Conference_Titel :
Electrical and Computer Engineering, 1996. Canadian Conference on
Conference_Location :
Calgary, Alta.
Print_ISBN :
0-7803-3143-5
DOI :
10.1109/CCECE.1996.548069
