Modeling and co-simulation of I/O interconnects for on-chip and off-chip EMI prediction

Author

Kwak, SangKeun ; Jo, Jeongmin ; Kim, SoYoung

Author_Institution

Dept. of Semicond. Syst. Eng., Sungkyunkwan Univ., Suwon, South Korea

fYear

2012

fDate

21-24 May 2012

Firstpage

821

Lastpage

824

Abstract

In this paper, modeling and co-simulation methodology is proposed to predict EMI noise from the switching activity of on-chip interconnects. The proposed model includes the model for I/O driver and the on-chip interconnect load, the PKG and the test PCB, and the conducted and radiated EMI simulation. Using the simulation results of the proposed model, the I/O driver and the interconnect design can be optimized for minimum chip level EMI noise.

Keywords

driver circuits; electromagnetic interference; integrated circuit interconnections; integrated circuit modelling; printed circuit testing; EMI conduction simulation; EMI radiation simulation; I-O driver; I-O interconnect cosimulation; I-O interconnect modeling; PKG; interconnect design; on-chip interconnect load; on-chip-off-chip EMI noise prediction; switching activity; test PCB; Electromagnetic interference; Integrated circuit modeling; Load modeling; Semiconductor device modeling; Solid modeling; System-on-a-chip; Voltage measurement; EMI; I/O driver; ICs; Interconnect; Switching current;

fLanguage

English

Publisher

ieee

Conference_Titel

Electromagnetic Compatibility (APEMC), 2012 Asia-Pacific Symposium on

Conference_Location

Singapore

Print_ISBN

978-1-4577-1557-0

Electronic_ISBN

978-1-4577-1558-7

Type

conf

DOI

10.1109/APEMC.2012.6237995

Filename

6237995