Structural optimization of fine pitch, large die flip chip package

Author

Viswanath, Akella G K ; Fang, Wang ; Chai, Tai-Chong ; Khan, Navas ; Sampath, Srinivasamurthy

Author_Institution

Inst. of High Performance Comput., Singapore

fYear

2004

fDate

8-10 Dec. 2004

Firstpage

105

Lastpage

108

Abstract

In this paper we focus on the structural optimization of fine pitch, large die flip chip package by thermo mechanical analysis. At first the type of buildup substrate design that has to be used for this package is selected by conducting a comparative study of effect of four core substrate layer (2-4-2) and a two core substrate layer (2-2-2) on the overall stress distribution of the package. Second, an optimization study of package dimensions (the heat spreader dimensions, die chamber angles, structural adhesive thickness and bump size) is conducted with emphasis on the shear stress occurring at the die corner and warpage of the overall structure

Keywords

flip-chip devices; optimisation; thermomechanical treatment; bump size; die chamfer angles; fine pitch; four core substrate layer; heat spreader dimensions; large die flip chip package; overall stress distribution; package dimensions; shear stress; structural adhesive thickness; structural optimization; thermo mechanical analysis; two core substrate layer; Electronic packaging thermal management; Electronics packaging; Finite element methods; Flip chip; High performance computing; Microelectronics; Parametric study; Performance analysis; Temperature distribution; Thermal stresses;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics Packaging Technology Conference, 2004. EPTC 2004. Proceedings of 6th

Conference_Location

Singapore

Print_ISBN

0-7803-8821-6

Type

conf

DOI

10.1109/EPTC.2004.1396586

Filename

1396586