Fine pitch micro-bump Cu/Sn solid state diffusion bonding with and without surface planarization

3D integration requires a physical stacking of die onto another die while forming a permanent electrical and mechanical connection between the input/output pins of the devices. Low temperature stacking of dies for 3D integration has been gaining interest due to the thermal sensitivity of some advanced node devices such as DRAM. This paper presents a systematic study of Cu/Sn solid state diffusion bonding. This includes the use of bump surface conditioning and surface planarization. The Cu/Sn solid state diffusion bonding together with Cu TSV is used for making die to die vertical interconnection.