Gate dimension characterization using the inversion layer

A novel technique is presented to characterize the bottom and cross sectional dimensions of a metal-oxide semiconductor (MOS) gate based on measuring the inversion layer linewidth. The results presented are taken from a structure fabricated in the Stanford 2- mu m BiCMOS process. Analysis of test results revealed undesirable influences from three identifiable sources. Two are a result of different sheet resistances between the van der Pauw and Kelvin line portions of the structure. The third is due to small DVM currents, which drop a small voltage in the taps of the structure. A better layout based on this understanding is proposed. The bottom dimension of the gate can potentially be used in conjunction with other measurements of the gate, such as the width of the selective tungsten, in order to predict the cross-sectional shape of the gate or tungsten selectivity.