Analysis of the determination of the dimensional offset of conducting layers and MOS transistors

Author

Swaving, Sieger ; Van der Klauw, Kees L M ; Joosten, Jos J M

Author_Institution

Philips Res. Lab., Eindhoven, Netherlands

fYear

1989

fDate

13-14 March 1989

Firstpage

15

Lastpage

21

Abstract

In VLSI processes, dimension control is of vital importance. It is therefore essential to know the limitations of the methods to determine the dimensional offsets. The authors give a straightforward quantitative analysis of some of the present methods. It shows very clearly that large errors are made if the effects of certain error sources on the determination of dimensional offsets are not taken into account. The analysis is applied to the determination of the width offset of conducting layers and the determination of the metal-oxide semiconductor transistor channel length offset.

Keywords

VLSI; insulated gate field effect transistors; integrated circuit technology; measurement errors; metallisation; semiconductor device testing; spatial variables measurement; MOS transistors; VLSI processes; channel length offset; conducting layers; dimension control; dimensional offset; error sources; width offset; Contact resistance; Electrical resistance measurement; Equations; Fabrication; Geometry; Laboratories; MOSFETs; Resistors; Solid modeling; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronic Test Structures, 1989. ICMTS 1989. Proceedings of the 1989 International Conference on

Print_ISBN

0-87942-714-0

Type

conf

DOI

10.1109/ICMTS.1989.39274

Filename

39274