Analysis of the determination of the dimensional offset of conducting layers and MOS transistors

In VLSI processes, dimension control is of vital importance. It is therefore essential to know the limitations of the methods to determine the dimensional offsets. The authors give a straightforward quantitative analysis of some of the present methods. It shows very clearly that large errors are made if the effects of certain error sources on the determination of dimensional offsets are not taken into account. The analysis is applied to the determination of the width offset of conducting layers and the determination of the metal-oxide semiconductor transistor channel length offset.