Title :
Parameter extraction for a SPICE II VDMOS model
Author :
Fernandez, J. ; Hidalgo, S. ; Berta, F. ; Paredes, J. ; Rebollo, J. ; Millán, J. ; Serra-Mestres, F.
Author_Institution :
CSIC-UAB, Barcelona, Spain
Abstract :
The authors describe the experimental procedures necessary to obtain the different parameters for a SPICE II VDMOS model, emphasizing the influence of the load resistance on the capacitive parameter extraction from a current analysis in the transient mode. These techniques have been applied to different fabricated interdigitated VDMOS structures, and good agreement has been obtained between SPICE II simulations and experimental data. The influence of a two-level gate oxide on the switching times is investigated.
Keywords :
capacitance measurement; electronic engineering computing; insulated gate field effect transistors; semiconductor device models; semiconductor device testing; voltage measurement; SPICE II VDMOS model; capacitive parameter extraction; current analysis; interdigitated VDMOS structures; load resistance; switching times; transient mode; two-level gate oxide; Capacitance; Capacitors; Circuit simulation; Driver circuits; Parameter extraction; Power integrated circuits; Power semiconductor devices; SPICE; Standards development; Voltage;
Conference_Titel :
Microelectronic Test Structures, 1989. ICMTS 1989. Proceedings of the 1989 International Conference on
Print_ISBN :
0-87942-714-0
DOI :
10.1109/ICMTS.1989.39277
