A timing driven approach for crosstalk minimization in gridded channel routing

The wire-to-wire spacing in a VLSI chip becomes closer as VLSI fabrication technology rapidly evolves. As a result, the reduction of crosstalk between interconnect wires becomes an important consideration in VLSI design. In this paper, we present a timing driven gridded channel routing approach for the minimization of crosstalk. Compared with previous works, the main distinction of our approach is that it enables timing driven routing with the objective of crosstalk delay minimization. Given an initial routing solution that was generated by a conventional channel routing algorithm, we construct a delay degradation graph for each pair of adjacent wires. Then, the reduction of crosstalk is carried out by reassignment, including dogleg, of horizontal wire segments. By iteratively improving the delay degradation graph, our goal is to satisfy crosstalk constraints on the nets and to minimize the total crosstalk constraints among all of the nets. Experimental data consistently shows that our approach achieves very good results.