DocumentCode
2598326
Title
A neural network approach for classifying test structure results
Author
Khera, D. ; Zaghoul, M.E. ; Linholm, L.W. ; Wilson, C.L.
Author_Institution
Nat. Inst. of Standards & Technol., Gaithersburg, MD, USA
fYear
1989
fDate
13-14 March 1989
Firstpage
201
Lastpage
204
Abstract
An approach is described for identifying and classifying semiconductor manufacturing process variation using test structure data. The technique uses a machine-learning algorithm based on neural networks to train computers to detect patterns associated with test structure results. The objective of this work is to develop more reliable machine-learning classification procedures using test structure data from a semiconductor manufacturing environment. An example based on characterizing the performance of a 1- mu m lithography process is presented as well as a description of the test chip.
Keywords
automatic testing; computerised pattern recognition; integrated circuit manufacture; integrated circuit testing; learning systems; neural nets; process control; IC manufacture; lithography; machine-learning algorithm; neural network; pattern detection; semiconductor manufacturing process variation; test chip; test structure; Artificial neural networks; Biological neural networks; Circuit testing; Electric variables measurement; Electronic equipment testing; Machine learning; NIST; Neural networks; Neurons; Semiconductor device testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Microelectronic Test Structures, 1989. ICMTS 1989. Proceedings of the 1989 International Conference on
Print_ISBN
0-87942-714-0
Type
conf
DOI
10.1109/ICMTS.1989.39309
Filename
39309
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