Realization of FPGA-based packet classification in embedded system

Multi-dimensional packet classification is often the performance bottleneck for network devices. For low-cost high performance embedded networking applications, the best solution could be doing packet classification by specially designed hardware which can effectively release the burden of system CPU. We have realized a compact FPGA-based packet classification coprocessor in an embedded system using MPC8260 under Linux operation system. High degree parallel architecture of the coprocessor allows it to run at line rate above 20 Gbps without packet losing. Furthermore, the coprocessor has deterministic search time and low memory consumption. By using Netfilter hooks in Linux network protocol stack MPC8260 manages the coprocessor to take the full charge of packet classification, so the performance of the system is not influenced much when multi-dimensional packet classification executed. The system described in this paper can be a good prototype developing platform for embedded networking applications.