Title :
Flipping structure: an efficient VLSI architecture for lifting-based discrete wavelet transform
Author :
Huang, Chao Tsung ; Tseng, Po-Chih ; Chen, Liang Gee
Author_Institution :
DSP/IC Design Lab., Nat. Taiwan Univ., Taipei, Taiwan
Abstract :
Using the lifting scheme to construct VLSI architectures for discrete wavelet transforms outperforms using convolution in many aspects, such as computation complexity and boundary extension. Nevertheless, the critical path of the lifting scheme is potentially longer than that of convolution. Although pipelining can reduce the critical path, it will prolong the latency and require more registers for a 1D architecture as well as larger memory size for a 2D line-based architecture. In this paper, an efficient VLSI architecture is proposed to provide a variety of hardware implementations for improving and possibly minimizing the critical path and memory requirements of lifting-based discrete wavelet transforms by flipping conventional lifting structures. By case studies of a JPEG2000 defaulted filter and an integer filter, the efficiency of the proposed flipping structure is shown.
Keywords :
VLSI; circuit CAD; circuit optimisation; circuit simulation; computational complexity; digital arithmetic; digital filters; discrete wavelet transforms; integrated circuit design; integrated circuit modelling; logic CAD; logic simulation; 2D line-based architecture; JPEG2000 defaulted filters; VLSI flipping structure architecture; boundary extension; computation complexity; convolution; critical path/memory requirement minimization; integer filters; latency; lifting scheme critical path; lifting-based discrete wavelet transforms; memory size; registers; Computer architecture; Convolution; Delay; Discrete wavelet transforms; Filters; Hardware; Image coding; Pipeline processing; Transform coding; Very large scale integration;
Conference_Titel :
Circuits and Systems, 2002. APCCAS '02. 2002 Asia-Pacific Conference on
Print_ISBN :
0-7803-7690-0
DOI :
10.1109/APCCAS.2002.1114975