A framework for specifying and designing pipelines

Author

Aagaard, Mark ; Leeser, Miriam

Author_Institution

Sch. of Electr. Eng., Cornell Univ., Ithaca, NY, USA

fYear

1993

fDate

3-6 Oct 1993

Firstpage

548

Lastpage

551

Abstract

We present a framework for designing control circuitry for pipelined circuits. Our framework supports any mixture of data-dependent, data-stationary and time-stationary control for pipelines with out-of-order execution. There are four parameters to the framework: (1) Protocol schemes describe how transactions are transferred between stages in the pipeline. (2) Arbitration schemes specify how to prevent and/or handle structural hazards in the pipeline. (3) Control schemes determine how transactions are routed through the pipeline and how stages know what operation to perform. (4) Ordering schemes describe a method for matching up transactions as they leave the pipeline with transactions that entered the pipeline. Based on our framework we have developed an algorithm for compiling the control circuitry for a wide class of pipelines from a high-level description of the schedule for the pipeline

Keywords

formal specification; logic design; pipeline processing; arbitration schemes; control circuitry; control schemes; data-dependent; data-stationary; out-of-order execution; pipelined circuits; Algorithm design and analysis; Circuit synthesis; Control system synthesis; Hazards; Microprocessors; Modems; Pipelines; Processor scheduling; Protocols; Scheduling algorithm;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Design: VLSI in Computers and Processors, 1993. ICCD '93. Proceedings., 1993 IEEE International Conference on

Conference_Location

Cambridge, MA

Print_ISBN

0-8186-4230-0

Type

conf

DOI

10.1109/ICCD.1993.393317

Filename

393317