Title :
A logic-level model for α-particle hits in CMOS circuits
Author :
Cha, Hungse ; Patel, Janak H.
Author_Institution :
Center for Reliable & High-Performance Comput., Illinois Univ., Urbana, IL, USA
Abstract :
Systems designed for reliability must be validated through simulations. However, traditional SPICE like simulators or even mixed-mode simulators are too slow for the task of simulating the effects of α-particle hits on relatively large circuits. Gate-level simulators offer tremendous speedup over these electrical level simulators, but they are only as good as the model which captures the α-particle effect at the logic level. The goal of this research is to develop a computationally efficient model which captures the behavior of the α-particle at the logic level. This model can then be used in a gate-level timing simulator to propagate the α-particle effects to the latches and the outputs of the circuit under simulation. We have developed a closed form solution to approximate the logic pulse waveform resulting from α-particle hits. As is presented in the paper, the model tracks the data from SPICE simulations remarkably well
Keywords :
CMOS integrated circuits; alpha-particle effects; circuit CAD; circuit analysis computing; integrated logic circuits; logic CAD; reliability; α-particle effect; gate-level timing simulator; logic level; reliability; simulations; Application software; CMOS logic circuits; Circuit simulation; Computational modeling; Latches; Pulse width modulation inverters; SPICE; Semiconductor device modeling; Very large scale integration; Voltage;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1993. ICCD '93. Proceedings., 1993 IEEE International Conference on
Conference_Location :
Cambridge, MA
Print_ISBN :
0-8186-4230-0
DOI :
10.1109/ICCD.1993.393319